1. Field of the Invention
The present invention relates to operation apparatuses that can be used in general-purpose microcomputers or the like, and more particularly, to improvement of an operation apparatus for digital signal processing.
2. Description of the Background Art
FIG. 1 is a block diagram of an operation apparatus that carries out processing of digital data disclosed in the copending application (U.S. Ser. No. 08/021,963). The copending application is incorporated herein by reference. Referring to FIG. 1, an operation apparatus receives digital data D1 and D2 of n bits, and an instruction code C of m bits respectively as packet data. In response, an operation is carried out to provide data D4 of n bits representing the operation result. The time period starting from entering data into an operation apparatus until the output of data representing an operation result of the input data is referred to as 1 instruction execution period time.
The operation apparatus includes an instruction decoder 21 for decoding an applied instruction code C for providing an operation control signal S5, a selection signal S2, and a rounding/no-rounding signal S4. The operation apparatus further includes a rounding unit 5 for carrying out a rounding process according to rounding/no-rounding signal S4 on input data of 2n bits for providing data D4 of n bits, an operation unit 6 including an adder-subtractor 11 for receiving in parallel data D1 and D2 and carrying out an operation in parallel according to operation control signal S5 to provide a data output, a logical operation unit 12, a multiplier 13 and a shifter 14, and a selector 7 for selecting one of a plurality of input data of 2n bits according to selection signal S2.
Operation control signal S5 includes a signal for switching adder-subtractor 11 to carry out either addition or subtraction, a signal specifying the logical operation contents of logical operation unit 12, or a signal specifying the amount and direction of shifting of shifter 14. Selection signal S2 serves to select and provide one of a plurality of data provided in parallel from operation unit 6 to selector 7. Rounding/no-rounding signal S4 is set to a signal that does not specify a rounding process when input instruction code C is a logical operation instruction code, and is set to a signal for specifying a rounding processing when other instruction codes C are input. The output data of each operation device in operation unit 6 is provided as data of 2n bits when applied to selector 7 from operation unit 6.
When an average of 2 data is to be calculated using the operation apparatus of FIG. 1, first, an add instruction is executed in adder-subtractor 11, whereby the addition resultant data is output from the operation apparatus as data D4. This addition resultant data D4 enters the operation apparatus again, and an instruction of shifting 1-bit rightward (a process of .div.2) is executed in shifter 14 of operation unit 6 to provide data D4. Thus, an average of two data is calculated. This operation process requires at least 2 instruction execution time periods for carrying out an add instruction and a shift instruction. This operation apparatus has a problem that a combined operation of an arithmetic operation and a shifter operation cannot be carried out at high speed.
When 100.times.3/4=75 is to be carried out by 2 instructions using a value converted into a two's complement notation of n=8 bits (value range-128 to 127) in the operation apparatus of FIG. 1:
1) at the first execution, a multiply instruction is carried out, and the result is rounded to 8 bit precision, 100.times.3=300--rounded to the maximum value by rounding unit 5.fwdarw.127;
2) a shifting operation is carried out at the next instruction execution,
127.div.4 (shifted rightwards by 2 bits) is carried out.fwdarw.31 (greatly differs from the logic value of 75).
When a multiplication+shift operation is carried out by the operation apparatus of FIG. 1, a problem set forth in the following occurs even when the eventual result of the multiplication+shift operation is within the range of the n bit precision. When the n bit precision is exceeded by the multiplication of the above 1), rounding unit 5 is used, and the above-described shift operation of 2) is carried out on an incorrect value rounded to a value that can be represented by n bit precision (a maximum value that can be expressed by n bits or a value having the digits exceeding n bits deleted). Thus, a logically correct operation result, can not be obtained.
A general DSP (Digital Signal Processor) is disclosed in pp. 1-2 in "Texas Instruments TMS320C30 DSP Preview Bulletin" issued by Texas Instruments. A block diagram of a CPU (Central Processing Unit) employed in this DSP is illustrated in page 2 of this literature. Although an ALU (Arithmetic Logical Operation Unit) and a shifter are arranged in series, a multiplier and a shifter are not arranged in series. It is therefore appreciated from the block diagram of this CPU that a combined operation process of multiplication and shifting requires at least 2 instruction execution time periods.
A high speed image processing DSP is disclosed in the Exhibition Product Guide Material of Panasonic's 1992 International Industry General Exhibition. This DSP is characterized in that a control circuit for a DCT (Discrete Cosine Transform) is provided. However, since a block structure is not employed taking into consideration a combined operation of an arithmetic operation and a shift operation, this DSP has disadvantages of requiring 2 instruction execution time periods for such combined operation, and a rounding error of a great level.
In an operation apparatus disclosed in Japanese Patent Laying-Open No. 60-54070, a shifter is employed for carrying out a rounding process when a value overflows in an arithmetic operation. However, there is no disclosure of using this shifter for a combined operation of arithmetic and shifting. Therefore, this operation apparatus has a disadvantage that a combined operation cannot be carried out in 1 instruction execution time period, leading to a problem that the operation speed cannot be increased.